收藏本站
3–16
Chapter 3: Functional Description
Device-Level Description
DLL Configurations
For Stratix series designs, IP Toolbench creates an instance of a DLL, which is
configured to match your controller. The DLL generates the 90 ° phase shift on the
DQS edges that capture the read data.
On Stratix devices, the reference clock is driven off the device and fed back into the
DLL reference clock inputs (refer to Figure 3–9 on page 3–15 ). If you turn on Insert
logic to allow the DLL to update only during the memory refresh period , the
controller generates a control signal, stratix_dll_control , which can enable the
DLL reference clock only while the controller is issuing refresh commands to the
memory.
On Stratix II devices, the DLL reference clock is fed directly from an enhanced PLL.
For an interface that is only on one side of the Stratix II device, the DLL automatically
generates a control signal, dqsupdate , to the DQS pins on the same side telling them
when it is safe to update their delay value. If your interface spans two sides of the
device, the controller can generate a control signal, stratix_dll_control , to only
allow the 6-bit control signal to each DQS pin to update only while the controller is
issuing refresh commands to the memory. Turning on Insert logic to allow the DLL
to update only during the memory refresh period causes the extra logic to be
inserted and should only be turned on if your interface spans two sides of the device.
Turning on this feature on a single sided interface is not required, because the DLL
controls the updates.
Table 3–4 shows the DLL signals.
Table 3–4. DLL Signals
Signal
clk
reset_n
delayctrlout
stratix_dll_control (1)
dqsupdate (1)
Description
The reference clock, which comes either from an external pin in Stratix devices or
from an enhanced PLL output in Stratix II devices.
The reset input.
The 6-bit output, which controls the value of the delay chain on the DQS inputs.
The control signal from the controller, which is available if you turn on Insert
logic to allow the DLL to update only during the memory refresh period . It
controls when the 6-bit control value to DQS pins updates. On Stratix devices
stratix_dll_control disables the clock output.
A DLL-generated control signal that controls when the 6-bit control value to DQS
pins updates, if the interface is only on one side of the device.
Note to Table 3–4 :
(1) Stratix II devices only.
Example Design
IP Toolbench creates an example design that shows you how to instantiate and
connect up the DDR or DDR2 SDRAM controller. The example design consists of the
DDR or DDR2 SDRAM controller, some driver logic to issue read and write requests
to the controller, up to two PLLs to create the necessary clocks and a DLL (Stratix
series only). The example design is a working system that can be compiled and used
for both static timing checks and board tests.
DDR and DDR2 SDRAM Controller Compiler User Guide
? March 2009 Altera Corporation
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
IP-SLITE2 IP SERIALLITE II
IP-SRAM/QDRII IP QDRII SRAM CONTROLLER
IP-VITERBI/SS IP VITERBI LOW-SPEED
IP4220CZ6,125 IC USB DUAL ESD PROTECT 6TSOP
IPA-66-1-600-10.0-A-01-T CIRC BRKR 10A 2POLE SCREW TERM
IPR-CSC IP COLOR SPACE CONVERTER RENEW
IPR-ED8B10B IP 8B10B ENCODER/DECODER RENEW
IPS-VIDEO IP VIDEO/IMAGE PROCESSING SUITE
相关代理商/技术参数
IP-SDRAM/DDR3 功能描述:开发软件 DDR3 SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/HPDDR 功能描述:开发软件 DDR SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/HPDDR2 功能描述:开发软件 DDR2 SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/LPDDR2 功能描述:开发软件 DDR2 SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPSE.4.33SM600 制造商:Banner Engineering 功能描述:FIBER IPSE.4.33SM600 GLASS FIBER (MIN ORDER 50)
IPSE.4.62SM600 制造商:Banner Engineering 功能描述:FIBER IPSE.4.62SM600 GLASS FIBER (MIN ORDER 50)
IPS-EMBEDDED 功能描述:开发软件 Embedded IP Suite MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPS-EVAL-EH-01 功能描述:ENERGY HARVESTING BOARD RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:THINERGY® 标准包装:1 系列:- 主要目的:数字电位器 嵌入式:- 已用 IC / 零件:AD5258 主要属性:- 次要属性:- 已供物品:板 相关产品:AD5258BRMZ1-ND - IC POT DGTL I2C1K 64P 10MSOPAD5258BRMZ10-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ100-ND - IC POT DGTL I2C 100K 64P 10MSOPAD5258BRMZ50-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ1-R7-ND - IC POT DGTL I2C 1K 64P 10MSOPAD5258BRMZ10-R7-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ50-R7-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ100-R7-ND - IC POT DGTL I2C 100K 64P 10MSOP